From Traditional Packaging to Advanced Packaging in PCB

TO

TO (Transistor Outline) is a type of transistor package designed to allow the leads to be molded and used for surface mounting. It is primarily made of plastic and metal. With the advancement of transistor applications, the TO package technology has also been rapidly developed.

The TO package consists of a TO base and a TO cap. The TO base serves as the foundation, providing power to the packaged component, while the cap facilitates smooth optical signal transmission. These two components together form a sealed package that protects sensitive semiconductor components.

DIP

DIP (Dual In-line Package) is a packaging format with fewer than 100 pins, suitable for through-hole soldering on PCBs, offering ease of operation. The pins of the DIP package extend from both sides, allowing it to be soldered directly into a chip socket with a specific structure or into a solder pad with the same number of holes. Its main advantage is the convenience of PCB through-holing and soldering, as well as better compatibility with the motherboard. The materials for DIP packaging are usually plastic or ceramic.

QFP

QFP (Quad Flat Package) is a type of package using the QFP technology where the distance between the pins is very small, and the pins are thin, generally numbering over 100. This packaging is suitable for large-scale or very large-scale integrated circuits. QFP must use SMT (Surface Mount Technology) to solder the chip to the motherboard. With SMT, there is no need to drill holes in the motherboard. The corresponding solder points are pre-designed on the motherboard surface, and aligning the chip’s pins with the solder points ensures successful soldering. Currently, QFP is widely used, and many MCU chips adopt this package.

SOP

SOP (Small Out-Line Package) is a common component form and a type of surface mount package. Its characteristic is that the leads extend from both sides of the package in a seagull-wing shape (L-shaped). Common packaging materials include plastic, ceramic, glass, and metal, with plastic being the primary material. SOP packaging originated in the late 1970s. Philips developed the small outline package SOP in 1968–1969. SOP packages are widely used, and derivative packaging types such as TSOP (Thin Small Out-line Package), VSOP (Very Small Out-line Package), and SSOP (Shrink Small Out-line Package) have since emerged.

BGA

BGA (Ball Grid Array) is a package where round or columnar solder balls are hidden underneath the package. After the 1990s, with the advancement of integration technology, BGA technology developed rapidly. Currently, high-density, high-performance, and high-frequency IC chips have adopted this packaging technology. BGA welding has attracted significant attention, especially in the manufacturing process of OEM electronic factories. The manufacturing capability of an OEM factory largely depends on the BGA welding quality.

COB

COB (Chip On Board) is an advanced integrated circuit packaging technology where the bare chip is directly mounted on the printed circuit board (PCB) and electrically connected via wire bonding. The chip is then encapsulated using materials such as epoxy resin to protect it. This packaging method is widely used in automotive electronics, medical devices, and consumer electronics due to its compact size, high performance, and strong reliability.

CSP

CSP (Chip Size Package) is an advanced packaging form where the package size does not exceed 1.2 times the size of the bare chip. CSP technology ensures that ultra-large scale integrated circuits are packaged with the smallest size, minimizing costs while maintaining high performance and reliability. CSP offers a significant reduction in package size compared to QFP and BGA, and it is expected to be the preferred packaging form for portable products that require the smallest possible size.

WLP

WLP (Wafer Level Packaging) involves packaging an entire wafer and testing it before cutting it into individual chips. The packaged chip size is identical to the bare chip. WLP allows ICs to be mounted face-down on a PCB using traditional SMT processes. The IC pads are directly soldered to PCB pads using independent solder balls. WLP technology provides small package size, low inductance between ICs and PCB, and a short production cycle.

2.5D Packaging

2.5D packaging involves assembling multiple IC chips on a shared substrate, typically using a silicon or organic interposer, to interconnect the chips and connect them to the external circuitry. This packaging technology helps enhance chip performance and reduce power consumption.

3D Packaging

3D packaging refers to the arrangement of components not just in the X-Y plane but also in the vertical Z direction. It reduces interconnection length, effectively uses three-dimensional space, improves packaging density, reduces volume, and saves material.

CoWoS

CoWoS (Chip On Wafer On Substrate) is a 2.5D integration technology where different chips are stacked on the same silicon interposer for interconnection. The CoWoS process allows chips to be connected to a wafer and then to a substrate, providing high interconnection density.

InFO

InFO (Integrated Fan-Out) is a cheaper version of CoWoS developed by TSMC, which replaces the silicon interposer with polyamide film material, reducing unit costs and packaging height. This technology has gained popularity in mobile applications and high-performance computing (HPC) markets.

SoIC

SoIC (System on Integrated Chip) is an innovative packaging technology developed by TSMC, combining CoWoS and multi-wafer stacking (WoW). It features a no-bump bonding structure, offering higher bump density, faster speed, and better performance with lower energy consumption.

EMIB

EMIB (Embedded Multi-Die Interconnect Bridge) is Intel’s attempt at 2.5D IC packaging. It eliminates the need for additional silicon interposers, instead connecting the chips with a small silicon bridge layer. EMIB allows high interconnection density, lower power consumption, and higher bandwidth.

Foveros and Hybrid Bonding

Foveros is Intel’s 3D packaging technology that enables the stacking and connection of different logic chips, combining various technologies, architectures, and memory modules. Hybrid Bonding allows for advanced 3D packaging with mixed process modules and enables more flexible, high-performance solutions.