PCB Stack Up

Engineers use a stackup to answer two connected questions: what does each copper layer do, and what separates the layers? A layer-order diagram answers the first. A material construction table answers the second. Both are needed before layout choices become manufacturing instructions.

Signal layers carry routed connections. Ground planes provide references and return paths. Power can be distributed through dedicated planes, routed conductors or copper regions, depending on the circuit. A layer labeled “signal” may also carry power, so the label alone does not describe every feature on it.

The physical construction normally combines these materials:

In glass-reinforced epoxy constructions, prepreg resin flows and cures during pressing. It fills the spaces around etched copper as well as bonding the stack. That is why a loose prepreg sheet description is not, by itself, a finished dielectric spacing.

This distinction also explains why two boards with the same layer count can have different thicknesses, impedances and manufacturing requirements.

Start at the top copper layer and work down through every copper and dielectric entry. Check the material description and thickness basis before adding values or using them in an impedance model.

An entry such as 3313 RC57% 4.2mil contains several pieces of information. The glass style identifies a reinforcement construction; RC describes resin content; the thickness text belongs to the material description. Those fields do not establish the complete resin system or guarantee a particular pressed thickness.

The 4-layer reference below lists that prepreg description alongside a thickness of 3.91 mil / 0.0994 mm. Read these as separate fields. Do not replace the listed spacing with 4.2 mil simply because that number appears in the material name. The relevant value for the proposed electrical model is the dielectric dimension confirmed for the manufactured construction.

The same care applies to 1080 RC67% 3.3mil in the 8-layer example. Glass style and resin content help describe the material; they do not form a universal lookup table for every supplier and pressing process.

One mil is 0.001 inch, or 0.0254 mm. Values rounded independently in mil and millimeters may differ slightly after conversion. Choose a controlling unit rather than mixing rounded columns in a calculation.

Also check where a dimension starts and ends. A dielectric spacing, a core including copper, and a complete board thickness are different measurements. Counting a core’s copper again can make an otherwise correct stackup appear too thick.

First consider the electrical layer arrangement; then examine the material construction. The functional examples below are possible arrangements, not fixed assignments for the material tables that follow. A suitable choice depends on routing, reference continuity, power distribution and the available dielectric spacings.

Two useful arrangements to evaluate are:

Arrangement A gives both outer routing layers a ground reference, while power must be distributed without a dedicated internal power plane. Arrangement B reserves a plane for power, but bottom-layer routing then requires careful review of its reference and return-current transitions. A split power region is not automatically a continuous reference for every trace above or below it.

The decision is therefore more specific than “four layers are enough.” Check the interfaces, routing density, power needs and reference changes together. Altium’s stackup discussion provides additional background on assigning electrical layer functions.

4-layer material construction reference

The core row excludes copper; L2 and L3 copper are listed separately. That distinction matters when calculating the total.

Six layers offer more room to distribute routing and power while keeping signals close to suitable references. One arrangement to assess is:

This arrangement uses two ground planes rather than assuming a dedicated power plane is mandatory. The actual dielectric spacings still matter: they determine coupling to the references and influence coupling between the inner routing layers. Other six-layer arrangements can allocate a dedicated power layer when the circuit requires it.

For dense BGA escape routing, additional layers may help, but layer count alone does not resolve via access or fabrication limits. Those decisions belong with the HDI PCB construction when an HDI structure is required.

6-layer material construction reference

This table describes two cores and three prepreg entries. It does not specify which copper layers your design must use for power or ground.

An 8-layer board gives more options for separating routing, power and reference layers. One possible electrical arrangement is:

Use the additional layers for a defined need, such as routing space, reference continuity or power distribution. Verify the dielectric spacings around each signal layer and how a signal changes reference when it changes layers. More layers do not compensate for routing across a plane gap or for an uncontrolled return path.

8-layer material construction reference

Where two prepreg plies appear between copper layers, both belong in the physical construction. They do not create an additional conductive layer.

Begin with the circuit’s routing and electrical requirements, not a preferred layer count. Component density, BGA escape paths, board dimensions and the interfaces on the board determine how much routing space is needed. Reference planes and power distribution then shape how that space can be used.

A signal connection needs a return path as well as a forward path. For fast transitions, a nearby continuous reference plane helps contain the field and control the current loop. Review the entire route, including layer changes and connector transitions, rather than checking only the layer label.

When a trace crosses a plane split, its intended return path can be interrupted. When it changes reference layers, the design needs a suitable return-current transition. The board’s grounding and decoupling strategy must support that transition; simply assigning an adjacent layer as “power” does not establish a satisfactory reference everywhere.

Check physical balance around the board’s center: core and prepreg arrangement, dielectric thicknesses, and copper distribution all deserve review. Electrical layer names do not have to mirror each other for the physical construction to be balanced.

Consider via requirements early. Through holes, blind or buried vias, and microvias can require different constructions and lamination sequences. A reference stack for a conventional through-hole board should not be reused unchanged for a sequential-lamination HDI design.

The useful sequence is to propose layer functions, check the routing and references, and then confirm that the materials and manufacturing process can produce the required geometry.

Material selection involves more than choosing “FR-4.” The laminate and prepreg system, dielectric behavior, thermal requirements and construction must suit the design. Loss-sensitive RF and high-speed designs may require a closer material comparison; the high-frequency material selection guide covers that decision in more detail.

Three values can appear in a stackup discussion:

• Nominal board thickness: the target used for mechanical fit or ordering.
• Listed construction thickness: the dimensions assigned to the copper and dielectric entries in a proposed stack.
• Finished thickness requirement: the dimension and tolerance accepted on the completed board, measured on the agreed basis.

They must be reconciled before production. A sum of reference entries is a useful check, but it is not a measurement of a finished board.

Adding the millimeter values in the material tables above gives:

These are arithmetic totals of the displayed values. They do not add an assumed plating allowance, solder-mask allowance or manufacturing tolerance. A production drawing must state the finished target and clarify which layers and coatings are included in its thickness definition.

For prepreg, use the fabricator’s proposed pressed thickness. Resin flow, copper coverage and the selected material/process affect the resulting dielectric. There is no single percentage reduction that should be applied to every 1080 or 3313 sheet.

Copper weight is commonly expressed in ounces per square foot; nominal 1 oz copper corresponds to approximately 35 μm. That conversion does not define the minimum copper remaining after processing.

In conventional constructions, inner-layer copper is patterned from the starting foil, while outer-layer processing can include plating. Cleaning and etching can also remove copper. State whether each requirement concerns starting foil, a finished target or an accepted minimum. Eurocircuits explains this distinction in its manufacturing guidance.

For example, the reference tables list inner copper at 0.0152 mm. Do not silently replace this value with a nominal ounce-to-thickness conversion. Confirm its meaning in the proposed construction, especially when copper thickness is used in an impedance or current-carrying calculation. Plated-hole copper is a separate requirement from planar copper thickness.

Two boards can share the same layer order and finished thickness yet need different trace geometries to meet the same impedance target. The relevant structure includes the signal’s reference layer, dielectric spacing and properties, copper geometry and, where applicable, solder mask and nearby copper.

Illustrative comparison: consider two proposed 4-layer boards, both nominally 1.6 mm thick. One places the top signal layer closer to L2 ground than the other. Even though the total thickness and layer count match, the same top-layer trace width need not produce the same impedance. The stackup and routing geometry must be evaluated together.

For differential routing, pair spacing is another input. Specify the target, the relevant layers and reference planes, and the required tolerance. Geometry calculated for one material construction should be reviewed if the material or dielectric thickness changes.

Our impedance control page explains the related manufacturing considerations. A layer diagram alone is not an impedance verification or a test report.