PCB Testing: Bare Board Inspection and Electrical Tests

A useful PCB test plan connects each manufacturing risk to a suitable check. A copper track can be broken, two separate networks can become bridged, or a hole can be outside its dimensional requirement. These problems need different evidence, even when they occur on the same board.

Consider a hypothetical board with two networks, A and B. A break in a track within A can interrupt a required connection. An unwanted copper bridge between A and B creates a connection the design did not intend. Electrical testing addresses those connection questions; optical inspection can also identify the physical shape of the break or bridge.

There is another possibility: a narrowed track still conducts electricity but falls outside the permitted geometry. That explains why an electrical pass and acceptable physical construction are separate requirements.

Testing becomes more useful when these results stay connected to the board revision and the requirement they verify. A general statement that a PCB has been “tested” provides less information than a defined method, scope and acceptance basis.

Visual inspection can identify surface damage, contamination, exposed copper, solder-mask misalignment and other visible conditions. Dimensional inspection checks features such as the outline, finished holes, slots, thickness and flatness against the drawing. The measurement method needs to suit the feature and its tolerance.

These checks matter before assembly. For example, an electrically correct board can still have a slot that does not fit its mating part or a mask opening that interferes with a soldering surface. A continuity result cannot resolve either problem.

The inspection plan should identify the critical features and how they will be evaluated. If a connector fit or a mounting location is especially important, mark it in the fabrication drawing rather than relying on a general note to “check all dimensions.”

Fabrication AOI examines visible PCB patterns using controlled lighting, imaging and a programmed reference. The images are aligned before the system evaluates differences such as missing copper, unwanted copper or conductor geometry outside the selected criteria. This Gerber-based image-comparison approach differs from checking component orientation or solder joints on an assembled board.

Inner-layer inspection happens while the copper is exposed. In a conventional multilayer process, the patterned inner cores can be inspected after etching and before lamination. Finding a defect at this stage allows its disposition to be decided before that pattern becomes buried in the stack. An optical scan of the completed board cannot look through the laminate to repeat the same inspection.

Outer-layer inspection checks the accessible outer patterns at the appropriate manufacturing stage. Inspection after pattern formation can reveal features that become harder to evaluate once later coatings are applied. Solder-mask inspection is another task, with its own reference features and inspection conditions.

An AOI indication is a location to investigate. Reflections, residue or surface appearance can produce a suspect image without proving a copper defect. An operator reviews the marked feature against the acceptance criteria and records the disposition. Cleaning, reinspection or any permitted corrective work should follow the controlled process rather than simply continuing until the image passes.

Recurring indications also provide manufacturing feedback. Repeated residual-copper indications in one area can prompt a review of the imaging or etching process. Keep the location and defect classification useful for that investigation, while retaining electrical testing for the required connectivity checks.

Bare-board electrical testing, also called E-test, evaluates the board’s conductive networks. It asks whether required connections are present and whether networks intended to remain separate satisfy the isolation requirement.

Continuity testing measures connections within a network. A broken track or an interrupted plated connection can prevent a required path from meeting the specified resistance limit. The test program and accessible measurement locations determine which paths are evaluated.

Isolation testing evaluates separation between networks under defined test conditions. An unintended copper bridge or another conductive path can cause a failure. The applicable resistance criterion and test voltage belong to the agreed test specification; the board’s normal operating voltage alone does not define them.

Probe contact is part of the measurement. Poor alignment, a contaminated contact surface or an unstable probe can produce an apparent failure that needs investigation. A passing retest is meaningful only after the suspected cause has been assessed and the required scope has been completed.

The public scope of IPC-9252B addresses electrical testing of unpopulated printed boards and explains that other checks are needed for physical characteristics. It also excludes embedded-component boards from that revision’s scope. Special resistive structures or embedded devices therefore need to be identified when the test strategy is discussed.

Electrical test data must correspond to the intended board revision. The fabrication package describes what will be manufactured; a design netlist identifies the intended electrical connections. Check their relationship before using the manufactured board’s test result as evidence of conformance.

A manufacturer can derive connectivity from production data, but a result against that reference does not independently prove that the production interpretation matches the designer’s intent. Where a separately exported CAD netlist is available, comparison can help expose a disagreement before the boards are released for manufacture.

For example, two copper areas may be connected in the artwork while the intended design treats them as separate nets. Testing against the artwork-derived reference alone could accept that connection. The useful next step is to resolve the data discrepancy and approve the correct revision, rather than adjust the test program to suppress the disagreement.

Identify intentional net ties, temporary panel connections and any special structures in the release notes. Board-level data and the production panel may represent those features differently. An agreed netlist format and consistent revision identifiers help engineering review the differences without guessing which dataset should take precedence.

Flying probes and dedicated fixtures provide different ways to contact a board. The electrical requirement still comes first: compare methods against the same required connections, isolation checks and acceptance conditions.

A flying-probe tester moves probes to programmed locations. It avoids a dedicated board-specific contact fixture, which can make it attractive for prototypes, changing designs and short production runs. Preparation still includes test-data validation, programming, positioning and contact planning.

A fixture-based tester uses a contact arrangement built for the board. A bed-of-nails fixture presents probes to many required locations, reducing repeated probe movement and supporting efficient testing of repeat builds. The fixture itself requires design, fabrication, verification and maintenance. Contacting many locations together does not necessarily mean every electrical measurement occurs simultaneously.

There is no single production quantity at which a fixture always becomes the better choice. Contact count, test scope, board complexity, handling and design stability change the comparison. Ask for setup and recurring costs to be separated when evaluating a quotation.

As a hypothetical example, a prototype expected to change its connector layout may benefit from flexible test preparation. A released design with frequent repeat orders may justify a dedicated fixture. Neither choice establishes the required electrical coverage by itself.

Bare-board fixture testing should also be distinguished from in-circuit testing (ICT) of a populated board. Both may use probes and fixtures, but assembled-board ICT can include component measurements and other checks that do not apply to an unpopulated interconnect. Our assembly testing page explains that later stage.

A track can pass a DC continuity test while its characteristic impedance is outside the required range. Transmission-line behavior depends on conductor geometry, reference planes and the surrounding dielectric construction. It cannot be established by a simple resistance reading.

For controlled-impedance designs, specify the target structures and measurement requirements. Time-domain reflectometry (TDR) can evaluate impedance using a suitable test structure and measurement setup. A representative coupon needs to reflect the relevant construction and conductor geometry; its relationship to the production board should be established in the test plan.

The PCB stackup defines the layer relationships behind those structures. Our impedance-control information provides the related manufacturing context. Include impedance requirements with the fabrication data so they can influence the construction and coupon plan before production.

Construction checks address a different set of questions. A microsection is prepared by cutting and polishing a selected specimen so features such as plated-hole walls, internal connections and layer construction can be examined. This is a local, destructive examination: the chosen location and specimen identity matter when interpreting the result.

Depending on the requirement, a panel coupon or a designated board specimen may be used. State what needs to be observed or measured and how the specimen represents the delivered construction. A section from one location is not automatically proof of every hole or interface on every board.

Where internal alignment or another suitable structural feature needs review, X-ray inspection may provide additional information. The inspection setup and the feature being examined determine its usefulness. It should not be treated as an automatic replacement for a required microsection or confused with the inspection of hidden solder joints after assembly.

Solderability testing evaluates whether specified surfaces can be wetted by solder under the selected procedure. Surface finish, handling, storage and the test method all affect the question being asked. The procedure needs an acceptance basis appropriate to the finish and application, rather than one universal temperature-and-time recipe.

Cleanliness may also be a specified requirement. Ionic residues can contribute to leakage or electrochemical problems under suitable moisture and electrical conditions. An extraction-based cleanliness measurement evaluates the chosen specimen and method; it does not identify every contaminant or establish long-term reliability by itself. Define the required cleanliness method and acceptance criterion instead of treating all chemical tests as interchangeable.

Thermal-stress and environmental testing investigate defined responses to exposure. Depending on the construction, the inspection may look for changes such as delamination or damage to plated connections after the specified stress. Temperature cycling, humidity exposure and mechanical testing should follow the product’s qualification or verification requirements.

These tests can require coupons, dedicated specimens or a sampling plan. Agree them before fabrication if sample preparation or additional lead time will be needed. Routine electrical testing, a solderability check and a reliability qualification are different activities; none should silently stand in for another on a purchase order.

The quality of a test result starts with preparation. A practical sequence keeps the design reference, the manufactured board and the acceptance decision connected:

1. Confirm the release. Match the fabrication files, drawing, reference data and test requirements to the same approved revision. Resolve ambiguous connections before programming the test.
2. Prepare the inspection and contact setup. Establish the relevant image references, test program, board positioning and accessible contact locations. Check the setup against the intended scope.
3. Perform the specified checks. Record results with the appropriate board, panel, specimen or lot identity. Keep measurements distinct from visual observations and any agreed exclusions.
4. Investigate indications or failures. Identify the affected feature or network, assess contact or imaging problems where relevant, and determine the disposition under the approved procedure.
5. Complete verification and records. Link authorized corrective work and any required retest to the original result. Confirm that the final records correspond to the delivered configuration.

When reviewing a report, check what the word “pass” applies to. A lot summary, a board-level E-test result and a coupon measurement contain different levels of detail. The required record format should follow the purchase requirement, including any program revision, sampling information, exceptions or traceability needed for the project.