PCB Power Layout
In electronic systems, the power supply is a critical module responsible for powering other functions. A well-designed PCB layout can optimize power efficiency, reduce heat dissipation issues, and minimize noise, ensuring accurate and stable power output. With increasing demands for miniaturization and intelligence in industrial, automotive, communication, and consumer products, power supply solutions must also meet these requirements. This article summarizes key considerations for on-board power PCB layout, providing guidelines for reference.
1. Power Supply Positioning
When designing on-board power supplies, it is essential to consider their placement early in the system layout. A key principle is to position the power supply close to the load to avoid long PCB traces that could cause significant voltage drops between the actual load voltage and the power supply’s output, affecting power accuracy, slowing dynamic load response, and reducing efficiency.
Moreover, it is crucial to estimate the power supply’s area correctly; otherwise, essential PCB layout rules may not be achievable, compromising the power supply’s performance. If the system includes fan cooling, placing the power supply near the exhaust can aid in heat dissipation and improve efficiency. Ensuring the effectiveness of fan cooling requires careful consideration of the heat dissipation path, ensuring that taller passive components (like inductors and electrolytic capacitors) do not obstruct the heat dissipation channel of shorter active components (such as MOSFETs and PWM controllers).
2. Multilayer PCB Design
In multilayer PCB designs, it is recommended to place a ground or DC voltage layer between high-current layers (such as input or output voltage) and sensitive small signal layers to serve as a shielding layer. The ground or DC voltage layer effectively isolates the sensitive small signals from power circuits, preventing interference. The basic principle for ground or DC voltage layer layout is to minimize routing, ensuring the entire layer remains intact and unsegmented. If routing is necessary, it should align with the power layer’s high-current routing direction to minimize interference.
| 6-Layer PCB | |
|---|---|
| Bad Layer Design | Recommended Layer Design |
| Layer 1 – Power components | Layer 1 – Power components |
| Layer 2 – Signal | Layer 2 – Ground plane |
| Layer 3 – Ground plane | Layer 3 – Signal |
| Layer 4 – DC voltage or Ground plane | Layer 4 – Signal |
| Layer 5 – Signal | Layer 5 – DC voltage or Ground plane |
| Layer 6 – Power components or controller | Layer 6 – Power components or controller |
| 4-Layer PCB | |
| Bad Layer Design | Recommended Layer Design |
| Layer 1 – Power components | Layer 1 – Power components |
| Layer 2 – Signal | Layer 2 – Ground plane |
| Layer 3 – Ground plane | Layer 3 – Signal |
| Layer 4 – Signal or controller | Layer 4 – Signal or controller |
3. Power Component Layout
Switching power supplies consist of power circuits and small signal control circuits. Power circuits include high-current components such as inductors, capacitors, and MOSFETs, which should be prioritized in the layout. Small signal control circuits include feedback resistors, compensation networks, frequency settings, and overcurrent settings, which are typically placed in specific positions on the power supply chip.
3.1 Power Trace Width Calculation
High current flows through power traces, and if the trace width is too narrow, it can increase trace resistance, leading to higher PCB temperatures. The following formula is suitable for calculating trace width for currents ranging from 1A to 20A, where W is the trace width in mils, I is the current in amps, and Tcu is the copper weight of the PCB in ounces. For example, with a 5A current and a copper weight of 1oz, the minimum trace width should be 120 mils.
3.2 High Current Rate of Change Loop Layout
All components, including PCB traces, have parasitic inductance, capacitance, and resistance. A high rate of change in current can induce voltage spikes across parasitic inductances, increasing component voltage requirements and radiating interference, thereby reducing the likelihood of passing EMI tests.
Figure 1 shows the basic structure of a Buck circuit, with the green line indicating the current path when the upper switch is on, and the red line showing the current path when the upper switch is off. The sections with only one color represent the high current rate of change loop. This method can be applied to all circuit topologies.
Figure 2 illustrates the high current rate of change loop in a Buck circuit, shown in blue. When laying out this loop, ensure that its ground and ground plane are separated and connected at a single point. The loop’s high-frequency decoupling capacitors typically range from 0.1uF to 10uF and are of the X5R or X7R ceramic type, which are preferred for their low parasitic inductance and resistance, providing a reliable path for the high current rate of change.
Figures 3 and 4 show the basic circuit structure and the high current rate of change loop in a Boost circuit, respectively. Similar methods of analysis and layout can be applied as with the Buck circuit.
3.3 High Voltage Rate of Change Node Layout
In switching power supplies, the node between the switching MOSFET and the freewheeling diode or synchronous rectifying MOSFET switches between ground and high voltage, with a high voltage rate of change. The ringing voltage at this node is a primary source of EMI noise. To prevent noise from coupling into noise-sensitive small signal circuits, the area of the switching node should be minimized. However, since this node carries high current, its copper area also aids in the heat dissipation of the MOSFET and diode, so it should not be too small.
In multilayer PCB designs, it is advisable to place a ground plane directly beneath the switching node for additional isolation, preventing noise propagation. In the case of SCT2360, the inductor L1 is placed close to the SW node, with the copper area of the SW node minimized while ensuring sufficient heat dissipation, thereby reducing noise propagation. Additionally, the loop connecting BST and SW is kept as small as possible, which is facilitated by the chip design, where SW and BST are placed on adjacent pins.
3.4 High-Frequency Filter Capacitor Layout
High-frequency filter capacitors are critical components that provide a path for high current rate of change loops and play a crucial role in reducing voltage stress. For example, in SCT2360, capacitor C3 should be placed as close as possible to the VIN PIN and PGND PIN of the chip, directly connected through short and wide traces.
High-Frequency Filtering Capacitor Layout Example (without Vias)
High-Frequency Filtering Capacitor Layout Example (with Vias)
3.5 Multiple Power Supply Layout
If a system has multiple power supplies sharing a single input source and these power supplies do not operate synchronously, the input power traces for each supply should be separated to prevent common-mode noise from propagating through the input and ground, causing mutual interference.
Conclusion
Eighty percent of power design issues originate from PCB layout problems. Investing sufficient time in PCB layout during the early stages can effectively reduce power debugging time later, shortening the overall development cycle. The SCT23xx series, with its optimized chip pin layout, assists customers in achieving optimal PCB layouts, leading to superior power performance.
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