Key PCB Design Rules

3W Rule

To reduce crosstalk between traces, the spacing between them should be sufficiently large. When the center-to-center distance between traces is at least three times the trace width, approximately 70% of the electric field remains unaffected by adjacent traces. This is known as the 3W rule. With a spacing of 10W, 98% of the electric field interference is prevented.

20H Rule

The electric field between the power layer and the ground layer can vary, causing electromagnetic interference (EMI) to radiate from the board edges—an effect known as the edge effect. To mitigate this, the power layer should be retracted inward, ensuring that the electric field remains within the ground layer. By retracting the power layer by 20H (where H is the dielectric thickness between power and ground), 70% of the electric field can be confined within the edge of the ground layer; retracting it by 100H confines 98% of the electric field.

5-5 Rule

When designing PCBs, a general guideline is that if the clock frequency exceeds 5 MHz or the rise time is less than 5 ns, a multilayer PCB should be used. In some cases, where cost considerations dictate the use of a double-layer board, it’s best to dedicate one side of the PCB as a complete ground plane.

Ground Loop Rule

To minimize loop areas formed by signal lines and their return paths, the loop area should be as small as possible. Smaller loop areas reduce external radiation and susceptibility to interference. Careful consideration of ground plane and critical signal trace distribution is necessary, especially in double-layer designs, where any available space should be filled with reference ground, and key signals should be isolated with ground lines.

Crosstalk Control

Crosstalk, the unwanted interference between adjacent traces, primarily arises due to the parasitic capacitance and inductance between parallel traces. Key strategies to mitigate crosstalk include:

• Increasing the spacing between parallel traces, following the 3W rule.
• Inserting grounded isolation traces between parallel lines.
• Reducing the distance between trace layers and ground planes.

Shielding Protection

Reducing signal loop areas also helps minimize interference. For critical signals, such as clock and sync signals, shielding may be necessary. This involves surrounding the trace with grounded lines and ensuring effective connection between the shielding ground and the actual ground plane.

Trace Direction Control

Adjacent layers should have orthogonal trace directions to avoid unnecessary interlayer crosstalk. If space is limited, particularly for high-speed signals, it is advisable to insert ground planes between routing layers to isolate signal lines.

Trace Open Loop Check Rule

Avoid open-loop traces, which can act as antennas and increase unwanted interference. Ensure that all traces are properly terminated and connected to prevent this issue.

Impedance Matching Check Rule

To avoid signal reflection, ensure that the trace width within the same network is consistent. Variations in trace width can cause uneven characteristic impedance, leading to signal reflection, which is particularly problematic at higher transmission speeds. Where unavoidable (e.g., at connectors or BGA package traces), minimize the length of inconsistent sections.

Trace Matching Rule

In high-speed digital circuits, if the PCB trace delay exceeds one-quarter of the signal rise time, the trace can be considered a transmission line. To ensure proper impedance matching between the input/output signals and the transmission line, various matching methods should be employed, depending on the network connection and routing topology.

Trace Closed Loop Check Rule

Avoid creating closed loops between signal traces on different layers. Such loops can cause radiation interference, a common issue in multilayer designs.

Trace Length Control Rule (Short Trace Rule)

Keep traces as short as possible, especially for critical signals like clock lines.

Chamfering Rule

Avoid right angles and sharp angles in traces.

Decoupling Capacitor Rule

Add necessary decoupling capacitors close to devices, ensuring the power passes through the capacitor before reaching the device.

Device Layout Partitioning/Layering Rule

Separate devices with different frequencies, typically placing high-speed components at the interface. Consider dividing the ground plane and connecting the two segments at a single point near the interface.

Isolated Copper Area Control Rule

Isolated copper areas can cause unpredictable problems. Connecting these areas to other signals, typically ground, can improve signal quality.

Power and Ground Layer Integrity Rule

In regions dense with vias, avoid connecting vias in a way that splits the power and ground layers, as this disrupts the plane’s integrity and increases signal loop areas.

Overlapping Power and Ground Layer Rule

Different power layers should not overlap in space to reduce interference between them, especially when the power levels differ significantly. If overlapping cannot be avoided, consider placing a ground layer in between.

Summary

This article outlines essential rules for PCB design, focusing on minimizing crosstalk, ensuring signal integrity, and preventing electromagnetic interference. Key concepts include the 3W and 20H rules, impedance matching, crosstalk control, and grounding techniques. Implementing these principles can significantly enhance PCB performance, particularly in high-speed and high-frequency applications. Proper application of these rules ensures a reliable and efficient PCB design, reducing noise, improving signal integrity, and enhancing overall functionality.